? Develop verification methodology and testbenches for digital and mixed-signal blocks
? Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnects
Basic Qualifications:
? BS, MS in Electrical Engineering, Computer Engineering, or related fields
? Experience:
? Local US lead is expected to have 10+ years of work experience in ASIC design verification
? Other engineers expected to have 2 to 5 years of work or academic experience in ASIC design verification
? History of assuming responsibility for a variety of technical tasks and completing projects independently
? Proficient in System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)
? Proficient in pre-synthesis, and post- place-and-route functional verification (NCSIM, VCS, ModelSim)
? Proficient in scripting or programming languages
? Experience working with version control software, such as Git
Preferred Qualifications:
? Experience working on digital designs with multiple clock domains and clock dividers
? Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
? Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
? Experience with verification of HBM memory interfaces (PHY and controller)
? Experience in formal model equivalence checking tools and verification methodology
? Programming experience in Python