Sr. Design Verification Engineer
Location: Cupertino, CA -onsite
Contract
Visa: ANY Visa is fine
3 open Position
Note: Candidate should be local to bay area -San Jose, CA
Job Description:
Position Overview: We are seeking a talented Design Verification Engineer to join our team. The ideal candidate will focus on verifying complex digital designs and ensuring they meet performance and specification standards.
Key Responsibilities:
- Develop and execute comprehensive verification plans and methodologies.
- Create, implement, and maintain testbenches using SystemVerilog, UVM, or similar frameworks.
- Collaborate with design teams to define verification requirements and ensure alignment with design specifications.
- Perform simulations, analyze results, and debug design issues to provide actionable feedback.
- Assess and report on coverage metrics to ensure thorough verification.
- Contribute to automation efforts to improve verification processes.
- Participate in design reviews, offering insights on design for testability.
Required Skills:
- Proficient in digital design verification methodologies, including UVM and SystemVerilog.
- Experience with simulation tools such as ModelSim, VCS, or Questa.
- Strong understanding of RTL design concepts and hardware description languages.
- Familiarity with assertion-based verification and formal verification techniques.
Experience:
- 3+ years of experience in design verification of ASICs or FPGAs.
- Proven track record working on chips across various technology nodes.
Technology Node Experience: 2nm to 14nm+
Largest Die Experience:2nm to 14nm+
Preferred Qualifications:
- MS or PhD in Electrical Engineering, Computer Engineering, or related field.
- Strong analytical skills and a collaborative mindset.
- Excellent communication skills.
If you are passionate about verifying cutting-edge digital designs and ready to contribute to innovative projects, we encourage you to apply!